Interrupts

The CPU hardware uses an interrupt request line wire which helps CPU to sense after executing every instruction. When the CPU checks that a controller has put a signal on the interrupt request line, the CPU saves a state, such as the current value of the instruction pointer, and jumps to the interrupt handler routine at a fixed address. The interrupt handler part determines the cause of the interrupt, performs the necessary processing and executes a interrupt instruction to return the CPU to its execution state.

The basic mechanism of interrurpt enables the CPU to respond to an asynchronous event, such as when a device controller become ready for service. Most CPUs have two interrupt request lines.

• non-maskable interrupt - Such kind of interrupts are reserved for events like unrecoverable memory errors.
• maskable interrupt - Such interrupts can be switched off by the CPU before the execution of critical instructions that must not be interrupted.

The interrupt mechanism accepts an address - a number that selects a specific interrupt handling routine/function from a small set.In most architectures, this address is an offset stored in a table called the interrupt vector table. This vector contains the memory addresses of specialized interrupt handlers.